The present invention relates in general to the fabrication of semiconductor light emitting devices (LED), and in particular, to an LED with improved luminance efficiency.
In a conventional LED, the light emitting structures is disposed on the surface of a substrate wafer comprising an active region sandwiched between upper and lower layer of opposite conductivity. The active region may contain multiple quantum wells (MQW) comprising alternating barrier layer and well layer to improve light generation efficiency. A blocking layer is also preferably included adjacent to the MQW to reduce the carrier leakage. In a GaN LED for example, the MQW contains GaN barrier layers and InGaN well layers in a blue LED. Typical substrates in the production of GaN LED are sapphire, SiC and Si. There are several issues in the conventional device. For example, there is a significant lattice mismatch of 13% and a thermal mismatch of −34% between GaN layer and sapphire. As a result, a stress is imposed in the thin GaN layer when registered on a thick sapphire substrate wafer. The strain energy continues to build up as the layer grows thicker. Beyond a critical thickness, the excess energy is relaxed and the lattice coherence between the layer and the substrate breaks down. This is accompanied by the formation of misfit dislocation defects in the vicinity of the substrate interface. The dislocation defect may find its way to thread into the active region during the high-temperature deposition of the upper layers. This would impair the light generation efficiency of the LED and adversely affect the performance of the device. The situation becomes worse in the GaN/Si materials system, which exhibits a lattice mismatch of 17% and a thermal mismatch of +100% between the GaN layer and the Si substrate wafer. In this case, the relaxation of the excessive strain energy often leads to the formation of micro cracks making the device inoperative. For reliable operation of the GaN LED especially when used in lighting applications, it is essential to achieve a high internal efficiency by keeping the defect level low in the device.
Special techniques using a strained layer superlattice has been attempted to amend the situation. For instance, the misfit dislocation defects may bend over at the interface and are refrained from propagating into the active region. Other methods such as selected area growth (SEG), epitaxial lateral overgrowth (ELO), pendeo-epitaxy and patterned sapphire substrate (PSS) have been demonstrated effective in the reduction of the misfit defects. Devices using the ELO and the PSS methods have been described for example, in U.S. Pat. No. 6,111,277 to Ikeda et al., and in U.S. Pat. No. 6,870,191 to Niki et al.
There are drawbacks in the prior art methods. In the context of the SEG and ELO methods, the layer is deposited through a seed window, or it is confined in a narrow channel. It often requires regrowth over multiple mask levels to block the dislocation defect. A single-step overgrowth is possible by growing the layers from a seed hole in a slit channel as described in U.S. Pat. No. 4,948,456 to Schubert et al. However, the layer growth through a slit is less predictable due to the difficulty of fast switching of source nutrients within the narrow space confined in the channel. Moreover, the build up of thermal stress in the overgrowing layer that adheres intimately to the mask would cause layer distortion and generation of extra defects. In the context of the PSS method, a dry etching or a wet etching process has been frequently employed to form patterns on the surface of a substrate wafer, e.g., a sapphire substrate wafer for the growth of a GaN LED. However, it remains a challenge to maintain a uniform etching profile across the substrate surface. The situation gets worse as the wafer size increases.